Sigma-delta (SD) converters, which operate in continuous-time mode, are also referred to as CTSD (Continuous-Time Sigma-Delta) modulators.
Such sigma-delta converters, which can operate at clock rates entering the gigahertz range, are intended to be used, inter alia, for achieving digitization of radio frequency analog signals directly at the antenna of mobile radio reception appliances which operate, by way of example, on the basis of the GSM (Global System for Mobile Communication), UMTS (Universal Mobile Telecommunication System) or WLAN (Wireless Local Area Network) standard.
The fundamental, limiting factor when implementing such high speed CTSD modulators is the jitter problem for the clock source, which is necessary in order to define feedback impulses in the CTSD. Since the energy in such a feedback pulse is proportional to the respective pulse width, any jitter influencing the rising or falling edges of the pulse supplies an undesirable noise contribution. Other limiting factors are the power consumption, the loop delay and the circuit's maximum operating speed, which is prescribed by the production technology. However, the last three limiting factors mentioned have recently been able to be avoided by the following methods:
At a theoretical level, the impulse invariance transformation method has been developed, which allows a discrete-time SD modulator to be mapped into a continuous-time circuit. This method takes into account the hold function which is provided by the DA converter in the SD modulator's feedback path and is based either on a full clock period or on half a clock period.
The availability of low submicron CMOS production processes with transit frequencies markedly above 100 GHz pushes the operating speed of such SD converters a long way upward.
Novel solutions in circuit design allow CTSD modulators to be implemented with a sensible power consumption.
The document “Continuous Time Sigma-Delta Modulators with Transmission Line Resonators and Improved Jitter and Excess Loop Delay Performance”, L. Hernandez, S. Paton, proposes an alternative theory for deriving a continuous-time SD modulator from a corresponding discrete-time model. In line with this theory, a CTSD converter's transfer function can be derived from that of a discrete-time modulator if the integrators in the continuous-time modulator are modeled using transfer lines. In this case, these are produced using quarter-lambda resonators. This printed document also infers that the equivalence between the two transfer functions means that the sensitivity toward jitter is reduced by orders of magnitude. This result is supported by simulations and a prototype with discrete components.
The fundamental drawback of the solution which arises in line with the document indicated above is that external transfer lines, namely the quarter-lambda resonators, are needed which are ceramic-quarter-lambda resonators in the present example. This not only makes this solution unattractive for mass production on account of high costs and the high space requirement for the external resonators but also means that the principle proposed is very sensitive toward mismatches between the electrical properties of the internal, namely integrated, and external components of the chip. In particular, problematical mismatches may arise between the quarter-lambda delay elements, which are produced by external transfer lines, and the clock rate of the clock generator, which defines the sampling rate for the quantizer in the SD converter's forward path.